1. Field of the Invention
The present invention relates to a semiconductor test interface, and more particularly, to a semiconductor test interface for performing a test of a semiconductor device by connecting the semiconductor device to be tested to the semiconductor test equipment.
2. Description of the Related Art
Generally, a test of a semiconductor chip is a final process for determining whether a complete product is a defective product. Semiconductor test equipments for effectively testing multiple products have been developed and are being used.
FIG. 1a is a diagram illustrating an example of a conventional semiconductor test equipment.
As shown, the conventional semiconductor test interface comprises a test body 110, a test head 120 and a semiconductor test interface 130, and one or more DUTs 140a through 140c are mounted on the semiconductor test interface 130 through a handler 150 so as to carry out a test.
Examples of the conventional semiconductor test equipment are disclosed in Korean Patent Application No. 10-2003-0016300 titled “SEMICONDUCTOR TESTER CAPABLE OF DECREASING A DUT BOARDQUANTITY AND ELECTRICAL TESTING METHOD THEREOF” filed by Samsung Electronics on Mar. 15, 2003 and published on Sep. 22, 2004, Korean Patent Application No. 10-2000-7009737 titled “COAXIAL PROBE INTERFACE FOR AUTOMATIC TEST EQUIPMENT” filed by Teradyne Incorporated on Sep. 2, 2000 and published on May 25, 2001, or Korean Patent Application No. 10-2002-7015270 titled “UNIVERSAL TEST INTERFACE BETWEEN A DEVICE UNDER TEST AND A TEST HEAD” filed by Advantest Corporation on Nov. 14, 2002 and published on Mar. 26, 2003.
In addition, a semiconductor test equipment having a motherboard 110 and a test head 120 integrated as a single body in order to reduce a dimension thereof has been developed. FIG. 1b illustrates another example of a conventional test equipment, wherein the semiconductor test interface 130 is mounted on a integrated test head 160 and DUTs 140a through 140c are then mounted on the semiconductor test interface 130 by a handler 150 so as to carry out a test.
Examples of the conventional integrated semiconductor test equipment are disclosed in Korean Patent Application No. 10-2004-45421 titled “SEMICONDUCTOR MODULE TEST EQUIPMENT FOR SIMULTANEOUSLY TESTING MULTIPLE SEMICONDUCTOR MODULES”” filed by the applicant on Jun. 18, 2004, or Korean Patent Application No. 10-2004-45422 titled “SEMICONDUCTOR COMPONENT TEST EQUIPMENT FOR SIMULTANEOUSLY TESTING MULTIPLE SEMICONDUCTOR COMPONENTS” filed by the applicant on Jun. 18, 2004.
FIG. 2a is a diagram exemplifying a semiconductor test interface used in a conventional test equipment or an integrated test equipment disclosed in Korean Patent Application No. 10-1997-0040701 titled “TEST BOARD FOR IC TESTER” filed by Ando Electric Co., Ltd. on Aug. 25, 1997 and published on Apr. 30, 1998.
As shown, the conventional semiconductor test interface disclosed in Korean Patent Application No. 10-1997-0040701 comprises a DUT unit 210 and a base unit 230.
While a DUT board 220 may comprise one or more connectors and one or more test sockets, description will be focused on a case of a single connector 225 and a single test socket 215.
The DUT unit 210 comprises the test socket 215 for mounting a DUT and the DUT board 220 having the connector 225 for a connection to a cable 240. The DUT board 220 is also referred to as a socket board.
While the base unit 230 may comprise one or more connectors and one or more cables, description will be focused on a case of connectors 235, 245 and 255 and the cable 240.
The base unit 230 comprises the connector 235 for a connection to the connector 225, the connector 245 for a connection to a base board 250, the cable 240, the base board 250 and the connector 255 for a connection to a connector 275 of a pin card 270 disposed in the test body. The pin card 270 is included in the test body or a test head, generates a test pattern for a test of the DUT to be output to the DUT (Device Under Test), and is referred to as various terms such as a pattern generating board.
In addition, FIG. 2b is a perspective view illustrating a combination of the base unit 230 and the pin card 270.
As shown, the base board 250 is an interface for transmitting an output signal from the pin card 270 to the DUT through the DUT unit 210. The base board 250 comprises the connector 255 for a connection to the connector 275 used for the pin card 270, and connectors 245a through 245x for an interface between connectors 225 used for a signal transmission to the DUT board 220 through a connection of the cable 240a. While the base board 250 also comprises multiple cables 240a through 240x and connectors 235a through 235x and 245a through 245x, these are identical to the connectors 235a and 245a and the cable 240a. Therefore, a detailed description is omitted.
As shown, an integrated connector having a large gap between long pins is used as a connector 275a generally used for the pin card 270 in order to facilitate a mechanical contact. Therefore, an integrated connector corresponding to the integrated connector having a large gap is used as the connector 255. In addition, the connectors 245a through 245x are configured to transmit a signal to a plurality of connectors 255 through the connectors 235a through 235x. 
The base board 250 comprises a circuit wiring for carrying out a signal interface between the connector 255 and the connector 245a because the structures of the connector 255 and the connector 245a through 245x are different.
The configuration disclosed in Korean Patent Application No. 10-1997-0040701 overcomes a disadvantage of conventional semiconductor test interface wherein a configuration of a DUT unit or a base unit thereof is complex, and a maintenance and high-speed transmission of high frequency signal are difficult due to a connection using a soldering or a pogo pin. In addition, the configuration disclosed in Korean Patent Application No. 10-1997-0040701 may correspond to a test of different types of DUTs by changing a connector housing of the connector 245 to change a connection line.
However, while the configuration disclosed in Korean Patent Application No. 10-1997-0040701 is advantageous in that the number of contact points such as a solder is less than the conventional configuration, it is disadvantageous to the high-speed signal transmission. Moreover, while the integrated connector is advantageous to a mechanical contact and support, the integrated connector is disadvantageous in that a high frequency wave characteristic is degraded. In addition, in accordance with an aspect of the maintenance of the semiconductor test equipment, since the semiconductor test equipment is divided into the base unit and the DUT unit, each of the units should be separately maintained, thereby making a manufacturing process more complex and increasing a manufacturing cost. Moreover, although the configuration may correspond to the test of the different types of the DUTs by changing the connector housing of the connector 245 to change the connection line, the connector housing of the connector 245 must changed one by one.
FIG. 2c is a diagram exemplifying another semiconductor test interface used in a conventional test equipment or an integrated test equipment disclosed in Korean Patent Application No. 10-2002-7015270 by Advantest Corporation.
Korean Patent Application No. 10-2002-7015270 discloses a configuration wherein a connector 228 is disposed below a DUT board 220 and is electrically connected to a connector 285 disposed in a board spacer 280 through a cable 240. An SCI (shielded controlled impedance), for example, is used as the connector 285, and the configuration is designed to have the number of the connector 228 less than that of the connector 285 so that the test of the different types of the DUTs may be carried out by changing only a connection between the connector 228 of the DUT board 220 and the connector 285.
However, in accordance with the configuration, a manufacturing cost is increased due to an addition of a board spacer 280 and a maintenance thereof is difficult. Moreover, the number of connector contacts is increased to degrade a high frequency wave characteristic. Since the number of the connector 228 does not correspond to that of the connector 285 by 1:1, that is the number of the connector 228 is smaller than that of the connector 285, the connector 228 of the DUT board 220 should be rearranged every time the DUT is changed.
It is very important that a configuration of the semiconductor test interface is simplified with respect to an operation of the semiconductor test equipment related to a high frequency signal processing since semiconductor test equipment processes multiple DUTs such as 256 or 512 DUTs currently.
Therefore, a demand for a semiconductor test interface wherein the high-speed transmission signal integrity is improved by minimizing the number of connector contacts and the maintenance of the semiconductor test equipment is facilitated by simplifying the semiconductor test interface is increasing.